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$34.99
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PmodCLS - Character LCD w/ serial interface
Connector(s):
Two 6-pin headers
  • 16x2 Character Display
  • Flexible communications using UART, SPI or TWI interface
  • Simple terminal-like display interface
  • Measures 3.75" x 1.75"
  • Ships with a 6" 6-pin cable, and a 6-pin header
The PmodCLS module can be used to display important debugging information during program development or as a user interface for completed designs. The module is ideally suited for projects built on Digilent embedded control boards, but can also be used with our FPGA-based boards.

For information on connecting this product using TWI, Click here. This product is a type A device.

Note:
There are two UART signal pin assignment conventions in use on Digilent products. This product uses the old signal assignment convention. Connecting a product using the old convention with one using the new convention requires the use of a UART Crossover Cable (not included). Click here for a more detailed explanation.







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$3.99
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UART Crossover Cable
  • 6", 6-pin crossover cable
  • Connects newer UART-interface Pmods (PmodBT) to older microcontroller boards (Cerebot 2, Cerebot 32MX4, etc.)
  • Connects older UART-interface Pmods (PmodCLS, PmodRS232, etc.) to newer microcontroller boards (Coming soon)
  • For more information on where / how to use this cable, please see this document.



Support Documents:

Doc # Date Categories Description  
DSD-0000153 Product Documentation PmodCLS Reference Manual Download
DSD-0000154 Product Documentation PmodCLS Schematics Download
DSD-0000347 2/01/12 Demonstration Project This zip file contains the chipKIT™ LCDS (Serial LCD) library files and example sketches for MPIDE. Download
DSD-0000385 9/07/12 Demonstration Project This zip file contains a Xilinx ISE demo project for the PmodCLS. This project was made for Xilinx ISE 14.2, targets the Nexys3, and is written in VHDL. Download
DSD-0000386 9/07/12 Demonstration Project This zip file contains a Xilinx ISE demo project for the PmodCLS. This project was made for Xilinx ISE 14.2, targets the Nexys3, and is written in Verilog. Download
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