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PmodCLP - Character LCD, parallel interface
Connector(s):
 One 6x2 pin header and one 6 pin header
  • 16x2 character display
  • Parallel data interface
  • Simple terminal like display interface
  • Measures 3.3" x 2.3"
  • Ships with a 6" 6-pin cable, a 6" 2x6-pin to dual 6-pin cable, and appropriate headers
The PmodCLP is a 16x2 character LCD module that uses two Pmod connectors to present a 3.3V, 8-bit parallel data interface to system boards. It is based on a Sunlike LCD panel that uses a Samsung KS0066 (or equivalent) LCD controller. The module can be attached to any number of Digilent system boards to create a character LCD subsystem.

NOTE: Revision A of the PmodCLP requires 5V for proper operation. This requires that the Pmod Headers used on the Digilent System board be set to 5V0 and not 3V3. All other Revisions utilize 3V3.






Support Documents:

Doc # Date Categories Description  
500-142 5/12/09 Product Documentation PmodCLP rev. A schematics Download
500-142B 5/12/09 Product Documentation PmodCLP rev. B schematics Download
502-142 Product Documentation PmodCLP Reference Manual Download
DSD-0000221 4/20/09 Reference Designs PmodCLP reference design Download
DSD-0000346 2/01/12 Demonstration Project This zip file contains the chipKIT™ LCDP (Parallel LCD) library files and example sketches for MPIDE. Download
DSD-0000354 2/29/12 Demonstration Project This zip file contains a library and MPLAB demo project for the PmodCLP. This project was made for MPLAB v8.83, targets the Cerebot MX4cK, and is written in C. Download
DSD-0000356 2/29/12 Demonstration Project This zip file contains a Xilinx ISE demo project for the PmodCLP. This project was made for Xilinx ISE 13.4, targets the Nexys3, and is written in VHDL. Download
DSD-0000383 9/07/12 Demonstration Project This zip file contains a Xilinx ISE demo project for the PmodCLP. This project was made for Xilinx ISE 14.2, targets the Nexys3, and is written in VHDL. Download
DSD-0000384 9/07/12 Demonstration Project This zip file contains a Xilinx ISE demo project for the PmodCLP. This project was made for Xilinx ISE 14.2, targets the Nexys3, and is written in Verilog. Download
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